1. Field of the Invention
This invention relates to memory subsystems and, more particularly, to write levelization mechanisms for memory subsystems.
2. Description of the Related Art
Various memory subsystem architectures are designed such that a memory clock signal and data strobe (DQS) signals generated by a memory controller arrive phase aligned at the corresponding memory devices to effectively perform read and write operations. In Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) and DDR2 SDRAM systems, the signals are phase aligned due, at least in part, to the fact that the trace lengths associated with the signals are matched. Since DDR3 SDRAM systems do not have matched trace lengths for these signals, DDR3 SDRAM memory architectures may include mechanisms for performing write levelization to phase align the memory clock signal and the DQS signals at the memory devices.